1. Field of the Invention
This invention pertains generally to digital computers and, more particularly, to a system and method for performing floating point operations in a digital computer.
2. Description of the Related Art
Floating point arithmetic is commonly employed in scientific and engineering computations in digital computers where high precision and large dynamic range are required. With floating point arithmetic, an operand or number is represented by a fraction which is called the mantissa, an exponent, and the sign of the mantissa. The mantissa is commonly written in a fixed point notation, e.g. one place to the left of the radix point, and the exponent is an integer which can be either positive or negative.
Depending upon the values of the operands, floating point addition and subtraction require some or all of the following steps: (1) calculation of the absolute value of the difference in the exponents of the two operands; (2) alignment of the two mantissas by shifting the mantissa of the smaller operand to the right by the number of places corresponding to the difference in the exponents; (3) addition or subtraction of the aligned mantissas; (4) two's complementing the difference if the difference is negative; (5) normalization of the sum or difference; (6) rounding of the normalized sum or difference; and (7) renormalization of the rounded sum or difference. At a minimum, an addition or subtraction operation generally requires alignment of the mantissas prior to the addition or subtraction step (prealignment), the addition or subtraction step itself, and normalization of the result of the addition or subtraction step (postnormalization). If the result of a subtraction is negative, then that result is complemented to provide a positive number which is normalized. The normalized result is then rounded and renormalized if the rounding has produced a carry from the most significant bit. Most of these steps involve propagation delays, which consume valuable processing time. The time elapsed from the beginning of one operation to the beginning an immediately following operation which is dependent on the first operation is referred to as the "latency" of the first operation, and latency is of critical importance in large, high speed arithmetic operations.
U.S. Pat. No. 4,639,887 describes a technique for improving the speed of a floating point addition or subtraction operation by breaking the three step process of prealignment, addition, and postnormalization into two parallel two step processes which are performed simultaneously in separate paths. This technique is based on the observation that depending upon the difference in the exponents of the operands, the addition or subtraction operation will consist essentially of either prealignment and addition or addition and postnormalization, but not both a large prealignment and a large postnormalization in the same operation. For an exponent difference greater than 1, postnormalization is eliminated, and the process consists essentially of prealignment and addition. For an exponent difference of 1 or less, prealignment is eliminated, and the process consists essentially of addition and postnormalization. Thus, the process in one path includes a prealignment shift of more than one place, addition, and a postnormalization shift of no more than one place, and the process in the other path includes a prealignment shift of no more than one place, addition, and a postnormalization shift of more than one place. Both of the processes are performed for each pair of operands even though only one of them will give a correct answer for any given pair, and the correct answer is selected as the result. Since only one large shift is required in each path, the overall processing time is significantly shorter than in the full three step process.